CMOS integrated circuits have become the most popular type of integrated circuits for logic, memory and microprocessors because they require little operating power. Low power is important for battery-powered equipment, such as watches, instruments, and laptop computers. CMOS manufacturing technology has improved over the last ten years, providing channel lengths in the sub-micron range. Therefore, CMOS low power advantages combined with faster device switching speeds, which are extremely important in computer applications, have made CMOS circuits competitive with older bipolar circuits.
The two primary requisites for CMOS integrated circuits are low power and high speed. However, these two requisites are generally in conflict. A CMOS circuit which is optimized for minimum power generally will be slower. Conversely, a CMOS circuit optimized for maximum speed will in most cases inherently draw more current and thus utilize more power. The speed/power relationship is much affected by manufacturing tolerances and varies from chip to chip within a wafer and from wafer to wafer. Typically, the actual speed and power of a particular chip cannot be determined until after the wafer has been completed, separated into individual chips and packaged in a plastic or ceramic package. At this stage, the chips coming off the production line are tested and separated into "bins" according to speed, power and perhaps also other parameters. The selection between higher-speed parts and lower-speed parts is called a "bin split." The highest price is usually obtained for the highest speed chips. However, chips which draw too much power are rejects. High-speed, low-power chips are like "U.S. Prime" beef compared to hamburger.
Unlike the manufacture of automobiles, however, where a "CHEVROLET" is started at the beginning of the assembly line and will continue to be a "CHEVROLET" until it emerges at the end, one does not know whether a semiconductor chip will turn out to be a "CHEVROLET" or a "CADILLAC" until the entire production cycle has been completed. A company expecting to produce "CADILLACS" and ending up mostly with "CHEVROLETS" will, in all likelihood, go broke. A high speed chip usually is the "CADILLAC".
There have been several prior art attempts at tailoring the speed/power characteristics of a CMOS chip. One such method selects one of a set of multiple final metal masks rather than always use the same final mask. Each mask of this set of final masks is designed to make the correct connections among a set of resistors which control one or more primary current paths of the device to achieve a desired speed/power characteristic. The selected value of the resistor will control the current in the controlled current path and therefore affect the switching speed of the CMOS circuit. However, this additional operating current requires additional operating power. The selection of the final metal mask therefore determines the desired speed/power relationship.
An improvement on the above prior art method of controlling device speed/power characteristic has been to test the CMOS circuits at the wafer stage before the final metal mask step and before the device is encapsulated in its final package. Such a test is called an "E-test." The results of this E-test are used as an aid in selecting the final metal mask, as discussed above, to obtain the desired speed/power characteristic.
A prior art technique for saving standby power is to provide fuses on the wafer. Again prior to encapsulation, but in this case after the final metal mask step, one or more of these fuses is laser blown to disable parts of the device which are not needed, but otherwise would draw power. Again, however, the devices have only been tested at the wafer stage, not in their final packaging, when this laser adjustment step takes place. This introduces uncertainty in the results.
The main disadvantage of using different final masks or laser fuses to achieve different speed/power characteristics is inflexibility. After the devices have been finally packaged and tested, if they then fall outside the desired speed/power range, they are rejects and must be discarded. The selected mask or fuse permanently sets the final speed/power characteristics and there is no way, if the packaged device falls outside the desired range, to convert it to a device within the desirable range.
Even using the second technique of E-testing the device prior to final metal mask, it is known that E-tests are carried out on only a few locations on the wafer, and thus are inherently less reliable than final tests after encapsulation, when more complete testing can be done. As a result, many devices may no longer be within the desirable speed/power range after final encapsulation even though they appeared to have been within the desirable range at E-test. Moreover, if this E-test is done before the final metal mask step, the results will be even more suspect.
It would be much more desirable to fully test the CMOS integrated circuit after it has been finally encapsulated and be able then to adjust the speed/power characteristics. This invention enables a chip manufacturer to do just that--take a completed, packaged chip and adjust the speed/power characteristics of that chip without removing the chip from its final package.